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t b 6274 7a fg /afng/afnag/bfnag 200 9 - 01- 21 1 toshiba bi - cmos integrated circuit silicon monolithic t b 62747 a fg , t b 6274 7 a fng , t b 62747 a fnag , t b 62747 b fn a g 16- output constant current led driver the tb62747 series is comprised of constant - current drivers designed for leds and led panel displays. the regulated current sources are d esigned to provide a constant current, which is adjustable through one external resistor. the tb62747 series incorporates 16 channels of shift registers, latches, and gates and constant - current outputs. fabricated using the bi - cmos process, the tb62747 ser ies satisfies the system requirement of high - speed data transmission. the tb62747 series is rohs compatible features ? power supply voltages: v dd = 3.3 v to 5 .0 v ? 16- output built - in ? output current setting range : 1.5 to 3 5 ma @ v dd = 3.3 v , v o = 0.4 to 1.0 v : 1.5 to 45 ma @ v dd = 5.0 v , v o = 0.4 to 1.2 v ? constant current output voltage: v o = 26 v (max) ? current accuracy (@ r ext = 1. 2 k ? , v o = 0.4 v, v dd = 3.3 v, 5.0 v ) : between outputs: 1.5 % ( max ) : between devices: 1.5 % ( max ) ? fast respons e of output current : t woe(l) = 100 ns (min) ? control data format: serial - in, parallel - out ? input signal voltage level: 3.3 v and 5 v c mos interfaces (schmitt trigger input) ? serial data transfer rate: 25 mhz (max) @cascade connection ? operation temperature ra nge: t opr = ? 40 to 85 c ? power on reset (por) ? package : a fg type : ssop24 -p-300- 1.00b : a fng type : ssop24 -p-300- 0.65a : a fnag type : p-s sop24 -0409-0. 6 4 - 001 : b fn a g type : p-s sop24 -0409- 0.6 4 - 001 t b 62747 a fg ssop24 - p - 300 - 1.00b t b 62747 a f n g ssop24 - p - 300 - 0.65a t b 62747 a f na g / b fn a g p - s sop24 - 0409 - 0.6 4 - 001 weight ssop24 -p-300- 1.00b : 0. 29 g ( typ. ) ssop24 -p-300- 0.65a : 0.14 g ( typ. ) p - s sop24 - 0409 - 0.64 - 001 : 0.14 g ( typ. )
t b 6274 7a fg /afng/afnag/bfnag 200 9 - 01- 21 2 pi n assignment ( top view ) note1 : short circuiting an output pin to a power supply pin (v dd or v led * ), or short - circuiting the r ext pin to the gnd pin will likely exceed the rating, which in turn may result in smoldering and/or permanent damage. please keep this in mind when dete rmining the wiring layout for the power supply and gnd pins. * v led : led power supply t b 6274 7afg/afng/a fnag t b 6274 7b fn a g out15 sout v dd r ext gn d sin sck slat out0 out1 out2 out3 out4 out5 out6 out7 v dd r ext sout oe out15 out14 out13 out12 out11 out10 out8 oe gnd sin slat out0 out1 sck out2 out3 out4 out5 out6 out7 out8 out9 out10 out11 out12 out13 out9 out14
t b 6274 7a fg /afng/afnag/bfnag 200 9 - 01- 21 3 block diagram out0 out1 constant current outputs out0 out1 out15 out15 16 - bit d - latch g q0 q1 q15 d0 d1 d15 r 16 - bit shift regist er q15 q0 q1 q15 r d0 slat oe sin sck por v dd gnd r ext sout b.g
t b 6274 7a fg /afng/afnag/bfnag 200 9 - 01- 21 4 truth table sck slat oe sin out0 out7 out15 *1 sout h l dn dn dn ? 7 dn ? 15 dn ? 15 l l dn + 1 no change dn ? 14 h l dn + 2 dn + 2 dn ? 5 dn ? 13 dn ? 13 ? *2 l dn + 3 dn + 2 dn ? 5 dn ? 13 dn ? 13 ? *2 h dn + 3 off dn ? 13 note1: when out0 to out15 output pins are set to "h" the respective output will be on and when set t o "l" the respective output will be off. note2: - is irrelevant to the truth table. timing diagram note 1: the latch circuit is a leveled - latch circuit. please exercise precaution as it is not triggered - latch circuit. note 2: keep the slat pin is set to l to enable the latch circuit to hold data. in addition, when the slat pin is set to h the latch circuit does not hold data. the data will instead pass onto output. when the oe pin is set to l the out0 to out15 output pins will go on and off in response to the data. in addition, when the oe pin is set to h all the output pins will be forced off regardless of the data. sin slat sck out0 out1 sout oe out15 h l n = 0 1 2 3 4 5 6 8 h l h l h l on off on off on off on off h l 7 9 11 10 12 13 15 14 2 out
t b 6274 7a fg /afng/afnag/bfnag 200 9 - 01- 21 5 pin functions pin no pin name i/o function a fg a fng a fnag b fnag 1 7 gnd ? the ground pin. 2 8 sin i the serial data input pin. 3 9 sck i the serial data transfer clock input pin. 4 10 slat i the lat ch signal input pin. data is saved at l level. 5 11 out0 o a sink type constant current output pin. 6 12 out1 o a sink type constant current output pin. 7 13 out2 o a sink type constant cur rent output pin. 8 14 out3 o a sink type constant current output pin. 9 15 out4 o a sink type constant current output pin. 10 16 out5 o a sink type constant current output pin. 11 17 out6 o a sink type constant current output pin. 12 18 out7 o a sink type constant current output pin. 13 19 out8 o a sink type constant current output pin. 14 20 out9 o a sink type constant current output pin. 15 21 out10 o a sink type constant current output pin. 16 22 out11 o a sink type constant current output pin. 17 23 out12 o a sink type constant current outpu t pin. 18 24 out13 o a sink type constant current output pin. 19 1 out14 o a sink type constant current output pin. 20 2 out15 o a sink type constant current output pin. 21 3 oe i the constant current output e nable signal input pin. during the h level, the outpu t will be forced off . 22 4 sout o the serial data output pin. 23 5 r ext ? the constant current value setting resistor connection pin. 24 6 v dd ? the power sup ply input pin.
t b 6274 7a fg /afng/afnag/bfnag 200 9 - 01- 21 6 absolute maximum rating s (t a = 25 c) characteristics symbol rating *1 unit power supply voltage v dd ? 0.4 to 6.0 v output current i o 55 ma logic input voltage v in ? 0.3 to v dd + 0.3 *2 v o utput voltage v o ? 0.3 to 2 6 v operating temperature t opr ? 40 to 85 c storage temperature t stg ? 55 to 150 c thermal resistance rth(j - a) 94 ( a fg ) *3 , 120 ( a fng ) *3, 80.07( a fnag/ b fn a g) when mounted pcb c/w power dissipation p d *4 1. 32 ( a fg ) *3 , 1.04 ( a fng) *3, 1.56 (afnag/bfnag) when mounted pcb w note1: voltage is ground referenced. note2: however, do not exceed 6v. note3: pcb condition 76.2 x 114.3 x 1.6 mm, cu 30 % (semi conforming) note4: the power dissipation decreases the reciprocal of the saturated thermal resistance (1/ rth(j - a)) for each degree (1c) that the ambient temperature is exceeded (ta = 25c). operating conditions dc items (unless otherwise specif ied, v dd = 3.0 to 5.5 v, t a = ? 40c to 85c) characteristics symbol test conditions min typ. max unit power supply voltage v dd ? 3.0 ? 5.5 v output voltage when off v o (on) outn 0.4 ? 4.0 v high level logic input voltage v ih sin,sck, slat , oe 0.7 v dd ? v dd v low level logic input voltage v il sin,sck, slat , oe gnd ? 0.3 v dd v high level sout output current i oh ? ? ? ? 1 ma low level sout output current i ol ? ? ? 1 ma constant current output i o1 outn , v dd = 3.3 v , v o = 0.4 to 1.0 v 1.5 ? 35 ma i o2 outn , v dd = 5.0 v , v o = 0.4 to 1.2 v 1.5 ? 45 ac items (unless otherwise specifi ed, v dd = 3.0 to 5.5 v, t a = ? 40c to 85c) characteristics symbol test circuit s test conditions min typ. max unit serial data transfer frequency f sck 6 ? ? ? 25 mhz hold time t hold1 6 ? 5 ? ? ns t hold 2 6 ? 5 ? ? ns setup time t setup1 6 ? 5 ? ? ns t setup 2 6 ? 5 ? ? ns maximum clock rise time t r 6 *1 ? ? 500 ns maximum clock fall time t f 6 *1 ? ? 500 ns note 1 : if the device is connected in a cascade and the tr/tf of the clock waveform increases due to deceleration of the clock waveform, it may not b e possible to achieve the timing required for data transfer. please keep these timing conditions in mind when designing your application.
t b 6274 7a fg /afng/afnag/bfnag 200 9 - 01- 21 7 electrical characteristics (unless otherwise specifie d, v dd = 3.3 v , t a = 2 5c) characteristics symbol test circuits te st conditions min typ. max unit high level logic output voltage v oh 1 i oh = ? 1 ma v dd ? 0.4 ? ? v low level logic output voltage v ol 1 i ol = + 1 ma ? ? 0.4 v high level logic input current i ih 2 v in = v dd , oe , sin, sck ? ? 1 a low level logic input current i il 3 v in = gnd, slat , sin, sck ? ? ? 1 a power supply current i dd1 4 v o = 25 v, r ext = open , sck = l , oe = h ? ? 1.0 ma i dd2 4 r ext = 1.2 k ? , all output off ? ? 4.0 ma i dd3 4 r ext = 1.2 k ? , all output on ? ? 8.0 ma output current i o 5 v dd = 3.3 v, v o = 0.4 v, r ext = 1.2 k ? , out0 to out15 ? 14 ? ma constant current error (ch to ch) ?i o 5 v dd = 3.3 v, v o = 0.4 v, r ext = 1. 2 k ? , out0 to out15 ? 1 1.5 % constant current error (ic to ic) ?i o(ic) 5 v dd = 3.3 v, v o = 0.4 v, r ext = 1. 2 k ? , out0 to out15 ? 1 1.5 % output off leak current i ok 5 v dd = 3.3 v, v o = 25 v, r ext = 1.2 k ? , out0 to out15 ? ? 0.5 a constant current po wer supply voltage regulation %v dd 5 v dd = 3.0 to 3.6 v, v o = 0.4 v, r ext = 1.2 k ? , out0 to out15 ? 1 2 % constant current output voltage regulation %v o 5 v dd = 3.3 v, v o = 0.4 to 3 .0 v, r ext = 1.2 k ? , out0 to out15 ? 1 ? %/v pull - up resistor r up 3 oe 250 500 800 k ? pull - down resistor r down 2 slat 250 500 800 k ? electrical characteristics (unless otherwise specifie d, v dd = 5.0 v , t a = 2 5c) characteristics symbol test circuits test conditions min typ. max unit high level logic output voltage v oh 1 i oh = ? 1 ma v dd ? 0.4 ? ? v low level logic output voltage v ol 1 i ol = + 1 ma ? ? 0.4 v high level logic input current i ih 2 v in = v dd , oe , sin, sck ? ? 1 a low level logic input current i il 3 v in = gnd, slat , sin, sck ? ? ? 1 a power supply current i dd1 4 v o = 25 v, r ext = open , sck = l , oe = h ? ? 1 .0 ma i dd2 4 r ext = 1.2 k ? , all output off ? ? 4.5 ma i dd3 4 r ext = 1.2 k ? , all output on ? ? 8.0 ma output current i o 5 v dd = 5.0 v, v o = 0.4 v, r ext = 1.2 k ? , out0 to out15 ? 14 ? ma constant current error (ch to ch) ?i o 5 v dd = 5.0 v, v o = 0.4 v, r ext = 1. 2 k ? , out0 to out15 ? 1 1.5 % constant current error (ic to ic) ?i o(ic) 5 v dd = 5.0 v, v o = 0.4 v, r ext = 1. 2 k ? , out0 to out15 ? 1 1.5 % output off leak current i ok 5 v dd = 5.0 v, v o = 25 v, r ext = 1.2 k ? , out0 to out15 ? ? 0.5 a constant current po wer supply voltage regulation %v dd 5 v dd = 4.5 to 5.5 v, v o = 0.4 v, r ext = 1. 2 k ? , out0 to out15 ? 1 2 % constant current output voltage regulation %v o 5 v dd = 5.0 v, v o = 0.4 to 3 .0 v, r ext = 1.2 k ? , out0 to out15 ? 1 ? %/v pull - up resistor r up 3 oe 250 500 800 k ? pull - down resistor r down 2 slat 250 500 800 k ?
t b 6274 7a fg /afng/afnag/bfnag 200 9 - 01- 21 8 switching characterist ics (unless otherwise specifie d, v dd = 3.3 v , t a = 2 5c) characteristics symbol test circuit s test conditions min typ. max unit propagation delay time sck - out0 t plh1 6 slat = h, oe = l ? 20 300 ns slat - out0 t plh2 6 oe = l ? 20 300 ns oe - out0 t plh3 6 slat = h ? 20 300 ns sck - sout t plh 6 cl=10.5 pf 10 20 35 ns sck - out0 t phl1 6 slat = h, oe = l ? 30 340 ns slat - out0 t phl2 6 oe = l ? 70 340 ns oe - out0 t phl3 6 slat = h ? 70 340 ns sck - sout t phl 6 cl=10.5 pf 10 20 35 ns output rise time t or 6 10 to 90% of voltage waveform ? 20 90 ns output fall time t of 6 90 to 1 0% of voltage waveform ? 25 180 ns enable pulse width t woe (l) 6 oe = l *1 1 00 ? ? n s clock pulse width t wsck 6 sck = h or l 20 ? ? ns latch pulse width t wslat 6 slat = h 20 ? ? ns note1: at the condition of t woe ( h ) = 25 0ns or more switching characterist ics (unless otherwise specifie d , v dd = 5.0 v , t a = 2 5c) characteristics symbol test circuit s test conditions min typ. max unit propagation delay time sck - out0 t plh1 6 slat = h , oe = l ? 20 300 ns slat - out0 t plh2 6 oe = l ? 20 300 ns oe - out0 t plh3 6 slat = h ? 20 30 ns sck - sout t plh 6 cl=10.5 pf 10 20 35 ns sck - out0 t phl1 6 slat = h , oe = l ? 30 340 ns slat - out0 t phl2 6 oe = l ? 70 340 ns oe - out0 t phl 3 6 slat = h ? 70 340 ns sck - sout t phl 6 cl=10.5 pf 10 20 35 ns output rise time t or 6 10 to 90% of voltage waveform ? 20 90 ns output fall time t of 6 90 to 1 0% of voltage waveform ? 25 180 ns enable pulse width t woe (l) 6 oe = l *1 100 ? ? n s clock pulse width t wsck 6 sck = h or l 20 ? ? ns latch pulse width t wslat 6 slat = h 20 ? ? ns note1: at the condition of t woe ( h ) = 25 0ns or more
t b 6274 7a fg /afng/afnag/bfnag 200 9 - 01- 21 9 i/o equivalent circuits 1. sck, sin 2. oe 3. slat 4. sout 5. out0 to out15 v dd sout gnd v dd (sck) (sin) v dd oe v dd slat gnd gnd out0 to 15 out gnd gnd
t b 6274 7a fg /afng/afnag/bfnag 200 9 - 01- 21 10 test circuit s sck sin oe v dd out0 out7 out15 sout gnd r ext i o = - 1ma to 1ma c l = 10.5 pf v dd = 3.3 v, 5.0 v f. g v ih = v dd v il = 0 v t r = t f = 10 ns (10 to 90%) slat test circuit1: high level logic input voltage / low level logic input voltage r ext v sck sin oe v dd out0 out7 out15 sout gnd r ext c l = 10.5 pf v dd = 3.3 v, 5.0 v slat te s t c ircuit2: high level logic input current / pull - down resistor r ext v in = v dd a a a a sck sin oe v dd out0 out7 out15 sout gnd r ext c l = 10.5 pf v dd = 3.3 v, 5.0 v slat test circuit 3 : low level logic input current / pull -up resistor r ext a a a a
t b 6274 7a fg /afng/afnag/bfnag 200 9 - 01- 21 11 test circuit4: power supply current test circuit5: constant current output / output off leak current / constant current error test circuit5: constant current power supply voltage regulation / constant current output voltage regulation sck sin oe v dd out0 r l = 300 ? c l out7 c l r l out15 c l = 10.5 pf r l sout gnd r ext c l = 10.5 pf v dd = 3.0 v, 5.5 v slat te s t circuit 6 : switching characteristics r ext = 1.2k ? f. g v ih = v dd v il = 0 v t r = t f = 10 ns (10 to 90%) v led = 4.9 v v o = 0.4 v, 25 v sck sin oe v dd out0 out7 out15 sout gnd r ext c l = 10.5 pf v dd = 3.3 v, 5.0 v slat f. g v ih = v dd v il = 0 v t r = t f = 10 ns (10 to 90%) a a a r ext = 1.2k ? sck si n oe v dd out0 out7 out15 sout gnd r ext c l = 10.5 pf v dd = 3. 3 v, 5.0 v slat r ext = 1.2k ? f. g v ih = v dd v il = 0 v t r = t f = 10 ns (10 to 90%) a v o = 0.4 v
t b 6274 7a fg /afng/afnag/bfnag 200 9 - 01- 21 12 timing waveforms 1. sc k, sin, sout 2. sck, sin, slat , oe , out0 3. oe , out0 10% 90% 10% 90% t or out0 off on 50% 50% 50% 50% t woe tplh3 tphl3 oe t of t woe(l) 50% t hold 2 sin sck 50% 50% 50% 50% t phl1 /t pl h1 t phl 2 /t pl h2 t wslat oe out0 50% slat 50% t setup2 t hold1 t plh /t phl t wsck 50% 50% 50% 50% t setup1 sin sck sout 50% 90% 10% t r t f 90% 10% t wsck 50%
t b 6274 7a fg /afng/afnag/bfnag 200 9 - 01- 21 17 reference data * this data is provided for referen ce only. thorough evaluation and testing should be implemented when designing your application's mass production design. output current C r ext resistor v dd =5 .0 v v o =1.0v t a = 25 c i out - r e xt 0 5 10 15 20 25 30 35 40 45 50 100 1000 10000 r e xt ( ? ) i out (ma) theoretical value i out ( a ) = 1.13 (v) r ext ( ? ) 14.9 all output on t a = 2 5 c v out =0 .7 v
t b 6274 7a fg /afng/afnag/bfnag 200 9 - 01- 21 18 reference data * this data is provided for reference only. thorough evaluation and testing should be implemented when designing your application's mass production design. output current C duty (led turn - on rate) i o - duty 0 5 10 15 20 25 30 35 40 45 50 0 20 40 60 80 100 duty - turn on rate (%) i o (ma) i o - duty 0 5 10 15 20 25 30 35 40 45 50 0 20 40 60 80 100 duty - turn on rate (%) i o (ma) i o - duty 0 5 10 15 20 25 30 35 40 45 50 0 20 40 60 80 100 duty - turn on rate (%) i o (ma) power dissipation C ta p d - ta 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 10 20 30 40 50 60 70 80 90 ta ( ) p d (w) ta = 2 5 q c v dd =5.0v v o =1.0v on pcb ta = 5 5 q c v dd =5.0v v o =1.0v on pcb ta =85 q c v dd =5.0v v o =1.0v on pcb afg af na g /bfnag a f n g af n g afg af na g /bfnag afg af na g /bfnag af n g af na g /bfnag afg af n g
t b 6274 7a fg /afng/afnag/bfnag 200 9 - 01- 21 19 package dimensions weight: 0. 29 g (typ.)
t b 6274 7a fg /afng/afnag/bfnag 200 9 - 01- 21 20 package dimensions weight: 0. 14 g (typ.)
t b 6274 7a fg /afng/afnag/bfnag 200 9 - 01- 21 21 package dimensions p - s sop24 - 0409 - 0.6 4 - 001 unit : inch weight: 0. 14 g (typ.) 0.337 to 0.344 0 .229 to 0. 244 0 .150 to 0. 157 0 .0325(ref ) 0 .025 0. 008 to 0. 012 0. 004 to 0. 098 0 .054 to 0. 068 0. 016 to 0. 034 0. 010(typ)
t b 6274 7a fg /afng/afnag/bfnag 200 9 - 01- 21 22 notes on contents 1. block diagrams some of the functional bl ocks, circuits, or constants in the block diagram may be omitted or simplified for explanatory purposes. 2. equivalent circuits the equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes. 3. timing ch arts timing charts may be simplified for explanatory purposes. 4. application circuits the application circuits shown in this document are provided for reference purposes only. thorough evaluation is required, especially at the mass production design sta ge. toshiba does not grant any license to any industrial property rights by providing these examples of application circuits. 5. test circuits components in the test circuits are used only to obtain and confirm the device characteristics. these components and circuits are not guaranteed to prevent malfunction or failure from occurring in the application equipment.
t b 6274 7a fg /afng/afnag/bfnag 200 9 - 01- 21 23 ic usage considerations notes on handling of ics [1] the absolute maximum ratings of a semiconductor device are a set of ratings that must no t be exceeded, even for a moment. do not exceed any of these ratings. exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result injury by explosion or combustion. [2] use an appropriate power supply fuse to ensure tha t a large current does not continuously flow in case of over current and/or ic failure. the ic will fully break down when used under conditions that exceed its absolute maximum ratings, when the wiring is routed improperly or when an abnormal pulse noise o ccurs from the wiring or load, causing a large current to continuously flow and the breakdown can lead smoke or ignition. to minimize the effects of the flow of a large current in case of breakdown, appropriate settings, such as fuse capacity, fusing time and insertion circuit location, are required. [3] if your design includes an inductive load such as a motor coil, incorporate a protection circuit into the design to prevent device malfunction or breakdown caused by the current resulting from the inrush current at power on or the negative current resulting from the back electromotive force at power off. ic breakdown may cause injury, smoke or ignition. use a stable power supply with ics with built - in protection functions. if the power supply is unstable, the protection function may not operate, causing ic breakdown. ic breakdown may cause injury, smoke or ignition. [4] do not insert devices in the wrong orientation or incorrectly. make sure that the positive and negative terminals of power supplies are connected properly. otherwise, the current or power consumption may exceed the absolute maximum rating, and exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result injury by explosion or combustion. in addition, do n ot use any device that is applied the current with inserting in the wrong orientation or incorrectly even just one time. [5] carefully select external components (such as inputs and negative feedback capacitors) and load components (such as speakers), for example, power amp and regulator. if there is a large amount of leakage current such as input or negative feedback condenser, the ic output dc voltage will increase. if this output voltage is connected to a speaker with low input withstand voltage, overc urrent or ic failure can cause smoke or ignition. (the over current can cause smoke or ignition from the ic itself.) in particular, please pay attention when using a bridge tied load (btl) connection type ic that inputs output dc voltage to a speaker direc tly. points to remember on handling of ics ( 1 ) heat radiation design in using an ic with large current flow such as power amp, regulator or driver, please design the device so that heat is appropriately radiated, not to exceed the specified junction tem perature (t j ) at any time and condition. these ics generate heat even during normal use. an inadequate ic heat radiation design can lead to decrease in ic life, deterioration of ic characteristics or ic breakdown. in addition, please design the device taki ng into considerate the effect of ic heat radiation with peripheral components. (2) back - emf when a motor rotates in the reverse direction, stops or slows down abruptly , a current flow back to the motor s power supply due to the effect of back - emf. if the current sink capability of the power supply is small, the device s motor power supply and output pins might be exposed to conditions beyond maximum ratings. to avoid this problem, take the effect of back - emf into consideration in system design.
t b 6274 7a fg /afng/afnag/bfnag 200 9 - 01- 21 24
t b 6274 7a fg /afng/afnag/bfnag 200 9 - 01- 21 25 restri ctions on product use ? toshiba corporation, and its subsidiaries and affiliates (collectively "toshiba"), reserve the right to make changes to the i nformation in this document, and related hardware, software and systems (collectively "product") without no tice. ? this document and any information herein may not be reproduced without prior written permission from toshiba. even with toshiba's written permission, reproduction is permissible only if reproduction is without alteration/omission. ? though toshiba works continually to improve product's quality and reliability, product can malfunction or fail. customers are responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, softwar e and systems which minimize risk and avoid situations in which a malfunction or failure of product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. before customers use the product, create designs including t he product, or incorporate the product into their own applications, customers must also refer to and comply with (a) the latest versions of all relevant toshiba information, including without limitation, this document, the specifications, the data sheets and applicati on notes for product and the precautions and conditions set forth in the "toshiba semiconductor reliability handbook" and (b) the instruct ions for the application with which the product will be used with or for. customers are solely responsible for all asp ects of their own product design or applications, including but not limited to (a) determining the appropriateness of the use of this product in such d esign or applications; (b) evaluating and determining the applicability of any information contained in t his document, or in charts, diagrams, programs, algorithms, sample application circuits, or any other referenced documents; and (c) validating all operating parame ters for such designs and applications. toshiba assumes no liability for customers' product d esign or applications. ? product is neither intended nor warranted for use in equipments or systems that require extraordinarily high levels of quality and/or reliability, and/or a malfunction or failure of which may cause loss of human life, bodily injury , serious property damage and/or serious public impact ( " unintended use " ). except for specific applications as expressly stated in this document, unintended use includes, without limitation, equipment used in nuclear facilities, equipment used in the aeros pace industry, medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to control combustions or ex plosions, safety devices, elevators and escalators, devices related to electri c power, and equipment used in finance - related fields. if you use product for unintended use, toshiba assumes no liability for product. for details, please contact your toshiba sales representative. ? do not disassemble, analyze, reverse - engineer, alter, m odify, translate or copy product, whether in whole or in part. ? product shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited unde r any applicable laws or regulations. ? the information contained herein is presented only as guidance for product use. no responsibility is assumed by toshiba for any infringement of patents or any other intellectual property rights of third parties that may result from the use of product. n o license to any intellectual property right is granted by this document, whether express or implied, by estoppel or otherwise. ? absent a written signed agreement, except as provided in the relevant terms and conditions of sale for product, and to the maximum extent allowable by law, toshiba (1) assumes no liability whatsoever, including without limitation, indirect, consequential, special, or incidental damages or loss, including without limitation, loss of profits, loss of opportunities, business interruption and loss of data, and ( 2) disclaims any and all express or implied warranties and conditions related to sale, use of product, or information, including warranties or conditions of merchantability, fitness for a particular purpose, accuracy of information, or noninfringement. ? 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